Next Generation Patterning Technology for Sub-10nm Device

Time 2015-11-12 14:30~15:00 Place Room 603+604
Code No. FB-I12 Session Chair
Name Prof. Myoungsoo Kim
Affiliation Korea University
Title Next Generation Patterning Technology for Sub-10nm Device
Contents
The semiconductor manufacturing moves toward the 7nm node for logic and 15nm node for memory. The scaling down to sub-10nm is more important and difficult situation than before. The traditional patterning source and technology have confronted to their limited resolution and process steps. Now, the next generation patterning technologies of EUV, DSA and nanoimprint are much focused for sub-10nm patterning. This paper will give a talk about the development status and the application possibility for high volume manufacturing (HVM) of these technologies. And also, they are compared with ArFi SAMP currently using for sub-20nm fine patterning in the respect of process step and cost. Even though EUV has showed the better lithographic performance than other technologies, it needs more development time for HVM application because of the power-up delay. And the characteristics of DSA patterning using a thermodynamic property of co-polymer and the nanoimprinting which can be patterned without exposure tool will be also investigated in this presentation. It is expected that the mixtures of these technologies or sole technology will be applied for specific layers of sub-10nm pattern size after considering the process margin, process step and cost for HVM in the near future.